Thermal CVD of Silicon Nitride
Thermal silicon nitride is generally produced using a tube reactor operating at low pressures. Dichlorosilane, SiCl2H2, is a common precursor, with silane also being used. The oxidant is ammonia. Typical conditions are between 700 and 800 °C, at around 1 Torr; deposition rates are in the 10 nm/minute range, but many applications employ very thin films, so throughput is reasonable in batch processing.
The resulting films are dense and hard, and also highly stressed: 1010 dynes/cm2 is typical. The films are excellent barriers to just about everything, including hydrogen, although 4-8 atomic % H is generally incorporated. By varying the gas mixture, silicon-rich films can be produced. Conformality of the deposition is significantly better than e.g. silane oxides.
Hydrogen-free silicon nitride is nearly impervious to wet hydrofluoric acid (HF); thermal CVD films etch very slowly. Nitride films etch readily in fluorine-containing plasmas, and can be selectively etched with respect to silicon using hot (>150 °C) phosphoric acid.
The deposition process tends to produce copious amounts of powder in the exhaust system, in part due to the formation of NH4Cl (essentially an adduct of hydrochloric acid HCl and ammonia NH3).
Thermal CVD films have various applications in semiconductor fabrication. Nitride layers can be used as an etch stop for self-aligned contact holes, to allow lithographic misalignment to expose the polysilicon gate stack without excessive erosion during contact etch. Nitride layers can be used as a CMP (chemical mechanical polishing) stop layer for oxide polishing, and as a barrier to sodium diffusion to protect gate oxides. Deposited nitrides are frequently part of the dielectric stack for capacitors in DRAM (dynamic random access memory) fabrication processes, and sometimes used in gate dielectric stacks.
A few references:
"Distribution of Sodium in Silicon Nitride" I. Fränz and W. Langheinrich Solid State Elect 12 145 (1969)
"Low Pressure CVD Production Processes for Poly, Nitride, and Oxide", R. Rosler, Solid State Technology April 1977 p. 63
"Reliability study of thin inter-poly dielectrics for non-volatile memory application" S. Mori, Y. Kaneko, N. Arai, Y. Ohshima, N. Araki, K. Narita, E. Sakagami and K. Yoshikawa, IEEE Int'l Reliability Physics Symposium 1990 p. 132
"Dielectric Breakdown and Current Conduction of Oxide/Nitride/Oxide MultiLayer Structures" K. Kobayashi, H. Miyotake, M. Hirayama, T. Higaki and H. Abe, J Electrochem Soc 139 1693 (1992)
"Nitride-Masked Polishing (NMP) Technique for Surface Planarization of Interlayer-Dielectric Films" Y. Hayashi and S. Takahashi, Jpn. J. Appl. Phys. 32 1060 (1993)
"Four steps to a healthier vacuum system", H. Gatti, L. Laurin, Solid State Technology March 1997 p. 63 [vol 40 #3]
"Trends in DRAM Dielectrics" K. Tang, W. Lau and G. Samudra Circuits & Devices May 1997 p. 27
"Comprehensive downstream effluent management", Y. Gu and D. Hauschulz, Solid State Technology 1998
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